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synopsys inc (SNPS) Details

Synopsys, Inc. provides electronic design automation software products used to design and test integrated circuits (ICs). It offers Fusion Design Platform, a digital design implementation solution; Verification Continuum Platform that provides virtual prototyping, static and formal verification, simulation, emulation, field-programmable gate array (FPGA)-based prototyping, and debug solutions; and FPGA design products that are programmed to perform specific functions. The company also offers intellectual property (IP) solutions for USB, PCI Express, DDR, Ethernet, SATA, MIPI, HDMI, and Bluetooth low energy applications; analog IP, including data converters and audio codecs; and system-on-chip infrastructure IP, datapath and building block IP, and verification IP products, as well as mathematical and floating point components, and ARM AMBA interconnect fabric and peripherals. In addition, it provides logic libraries and embedded memories; configurable processor cores and application-specific instruction-set processor tools for embedded applications; IP subsystems for audio, sensor, and data fusion functionality; and security IP solutions. Further, the company offers Platform Architect tools for SoC architecture analysis and optimization; virtual prototyping solutions; and HAPS FPGA-based prototyping systems, as well as a series of tools used in the design of optical systems and photonic devices. Additionally, it provides security testing, managed services, programs and professional services, and training that enable its customers to detect and remediate defects in the software development lifecycle; manufacturing solutions for semiconductor manufacturers; and professional and other services. Synopsys, Inc. has collaboration with Palma Ceia SemiDesign, Inc. to provide ready-to-use NB-IoT solution; and Elektrobit to develop automotive electronic systems using virtual environments. The company was founded in 1986 and is headquartered in Mountain View, California.

13,245 Employees
Last Reported Date: 12/17/18
Founded in 1986

synopsys inc (SNPS) Top Compensated Officers

Co-CEO, President & Director
Total Annual Compensation: $2.9M
Co-Founder, Chairman & Co-CEO
Total Annual Compensation: $2.9M
Chief Financial Officer
Total Annual Compensation: $1.2M
General Counsel & Corporate Secretary
Total Annual Compensation: $858.7K
Sales & Corporate Marketing Officer
Total Annual Compensation: $1.8M
Compensation as of Fiscal Year 2018.
synopsys inc
Faraday Technology Corporation Adopts Synopsys, Inc.'s SpyGlass Design Handoff Kit to Ensure High Design Quality

Synopsys, Inc. announced that Faraday Technology Corporation has adopted Synopsys' SpyGlass Design Handoff Kit. Faraday has deployed the SpyGlass Design Handoff Kit to ensure ASIC designs meet design quality requirements before initiating ASIC design service and production. The kit enables the required infrastructure for checking, reporting, and design packaging before handoff to the design service team. The software and methodologies needed to implement Faraday's IP and system-on-chip (SoC) design qualification requirements will also be integrated into the SpyGlass Design Handoff Kit. The SpyGlass Desgin Handoff Kit is available now.

Synopsys, Inc.'s Fusion Design Platform First to Be Certified by Samsung Foundry for 5LPE Process with EUV Technology

Synopsys, Inc. announced that Samsung Electronics has certified the Synopsys Fusion Design Platform™ for Samsung's 5-nanometer (nm) Low-Power Early (LPE) process with Extreme Ultraviolet (EUV) lithography technology. The AI-enhanced, cloud-ready Fusion Design Platform provides unprecedented full-flow quality-of-results (QoR) and time-to-results (TTR), enabling the full entitled performance and low power delivered by Samsung's 5LPE process technology to accelerate the next wave of semiconductor designs, including high-performance computing (HPC), automotive, 5G, and artificial intelligence (AI) market segments. Samsung Foundry certified the Fusion Design Platform using the 64-bit Arm® Cortex®-A53 and Cortex-A57 processors, which are based on the Armv8 architecture. Key tools and features of the Synopsys Fusion Design Platform optimized for Samsung 5LPE process technology include: Fusion Compiler™ RTL-to-GDSII Solution: Highly optimized full-flow support for latest 5LPE design rules delivering optimum design routability and convergence coupled to fastest TTR. IC Compiler™ II place-and-route: EUV single-exposure-based routing with optimized 5LPE design rule support, single fin variant-aware legalization, and via stapling to ensure maximum utilization while minimizing dynamic power. Design Compiler® Graphical and Design Compiler NXT RTL synthesis: Correlation, congestion reduction, pin access-aware optimization, 5LPE design rule support, and physical guidance for IC Compiler II. IC Validator physical signoff: Cloud-optimized physical signoff including DRC, LVS, and Fill. Innovative Explorer DRC and Live DRC technologies for enhanced productivity. PrimeTime® timing signoff: Near-threshold ultra-low voltage variation modeling, via variation modeling, and placement rule-aware engineering change order (ECO) guidance. StarRC™ parasitic extraction: EUV single pattern-based routing support, and new extraction technologies, such as coverage-based via resistance and vertical gate resistance modeling. RedHawk™ Fusion: ANSYS RedHawk-driven EM/IR analysis and optimization within place-and-route. Synopsys TestMAX™ DFT and Synopsys TestMAX ATPG test: FinFET-based, cell-aware, and slack-based transition testing for higher test quality. Formality® equivalence checking: UPF-based equivalence checking with state transition verification. Synopsys' Fusion Design Platform is in active production usage at market-leading companies; it redefines conventional design tool boundaries with the fusion of best-in-class optimization and industry-golden signoff and design-for-test (DFT) tools, enabling the most predictable full-flow convergence with the fewest iterations. The AI-enhanced platform boosts designer productivity by speeding up computation-intensive analyses and leverages past learning to achieve superior QoR. The Fusion Design Platform provides a streamlined cloud-ready design environment and is enabled on major public cloud providers' and Synopsys-hosted infrastructure.

Synopsys and GLOBALFOUNDRIES Collaborates to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process

Synopsys, Inc. announced its collaboration with GLOBALFOUNDRIES to develop a broad portfolio of DesignWare IP, including Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters, for GF's 12-nanometer (nm) Leading-Performance (12LP) FinFET process technology. Synopsys' DesignWare IP on the GF 12LP process enables designers to implement the latest interface and analog IP solutions in their artificial intelligence (AI), cloud computing, mobile, and consumer system-on-chips (SoCs) on GF's 12LP technology, which delivers a 10% improvement in logic density and more than a 15 percent improvement in performance compared to previous FinFET generations. This collaboration is another extension to the long-standing relationship between the two companies, which has delivered DesignWare IP for GF's processes from 180-nm to 12-nm.


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Price/Earnings 31.6x
Price/Sales 5.8x
Price/Book 4.8x
Price/Cash Flow 25.8x
TEV/Sales 5.5x

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